In modern telecommunication systems, it is often desirable to perform various signal processing functions such as echo cancellation, noise cancellation, and voice enhancement on signals received from telecommunication lines. As such, it becomes necessary to provide an interface between a telecommunication line and a digital signal processor capable of performing such functions.
One function of such an interface is to ensure proper signal synchronization. Incoming signals contain timing and synchronization information which can be distorted or lost during various signal processing functions. To ensure proper system operation, this signaling information must be accurately replaced prior to transmitting the processed signal. One approach to replacing lost signaling information is to insert signaling information into a particular bit of each frame in the signal. A problem with this method arises in T1 applications, where signaling information resides only in particular frames of the signal. Inserting signaling information into every frame of a T1 signal results in signal degradation as valid data is overwritten with signaling information. Another approach to replacing lost signaling information is to utilize a digital signal processor containing a synchronization algorithm to define the proper signaling frames. This approach is problematic, however, because adding such an algorithm to the digital signal processor itself would require implementing a myriad of complex logic resulting in increased expense.
In the interest of economy, telecommunication systems are often designed such that several system elements share a single digital signal processor. Where several system elements compete for a single digital signal processor, necessity dictates that the limited processing resources not be wasted by processing incomplete data or idle code. It therefore becomes desirable to detect the presence of incomplete data or idle code in the incoming signal, and to disable the digital signal processor with respect to those signals. In this way, the system's limited processing resources are conserved, leaving more resources available for the processing of incoming signals containing valid data.
One approach to detecting idle code is to compare the incoming signal to a fixed idle code pattern, such as "11111111." A disadvantage of this method is that fixed idle code patterns offer less system stability than a varied idle code pattern, such as "10101010." Further, a received signal may contain incomplete information, in other words less information than that originally transmitted. This may occur where the least significant bit of the received signal becomes "stuck" at "0" or "1." One approach to detecting this condition is to perform frequency analysis on the incoming signal. A disadvantage of this method is that it is complex and expensive to implement.